The present invention relates to telecommunications devices and more particularly, to a method and apparatus to permit access to and control over a greater number of PHYS than may be directly addressed using the Media Independent Interface protocol for direct PHY addressing.
Telecommunications devices such as bridges, routers and switches typically have a plurality of ports for connecting the device to different networks or subnetworks. Each port usually has at least one media access controller (MAC) for controlling access to the media in accordance with a predetermined network protocol. The MAC associated with a network protocol, such as the ethernet or fast ethernet protocol, interface to the physical media via logic which is known in the art as a PHY. The PHYS performs a number of interface functions. In particular, in the ethernet environment, the PHY performs a parallel to serial conversion of data forwarded by the MAC to the PHY and performs 4B to 5B encoding of such data to assure DC balance on the media. Furthermore, the PHY generates tri-level encoding of data, such as the MLT3 levels employed with 100Base-T. The PHY also receives the serial data stream from the media and converts the received serial data stream to a parallel data stream which is forwarded to the MAC. During the serial to parallel decoding, the PHY performs necessary 5b to 4b decoding of the received serial data stream.
The PHYS are controlled via a bidirectional serial management control bus such as the Media Independent Interface (MII) Management Interface specified in the IEEE Std 802.3u-1995 published by the Institute of Electrical and Electronic Engineers, Inc., New York, N.Y 10017 (2nd printing, Corrected Edition, Approved by the IEEE Standards Board Jun. 14 1995), which specification is incorporated herein by reference. The MII Management Interface Protocol is also described in a data sheet describing a commercially available component which is employed to implement PHYS in ethernet ports. The component is identified as the LXT970 Fast Ethernet Transceiver and is available from Level One Communications of Sacramento, California and is described in a data sheet bearing a copyright date of 1997, titled LXT970 Fast Ethernet Transceiver Data Sheet, which data sheet is incorporated herein by reference.
The MII Management Interface comprises a control bus and a protocol which permits the forwarding of control messages and information to a specified PHY from a processor and further permits the processor to access information within registers of PHYS coupled to the control bus. Each PHY which is coupled to the management control bus is assigned a five bit address which is used to identify the PHY. As a consequence of the five bit address limitation within the MII Management Interface specification, it is only possible to directly address 32 PHYS over a single management control bus. The five bit address limitation within the management control bus protocol presents an undesirable limitation on the number of PHYS which may be addressed via a single processor.
Port setup, management and statistics gathering operations within a telecommunications devices are often performed by an application processor which comprises a high-speed microprocessor. The processor employed to perform such functions is also typically employed to manage the PHYS within the device and thus must manage the transmission and reception of information over the management control bus. Burdening the processor with software control of the MII Management Bus operations can limit the available bandwidth of the processor to service and manage port configuration and statistics gathering functions. It would therefore be desirable to be able to allow a processor to manage the MII management bus transfers without using an inordinate amount of processor bandwidth for this purpose.